1. Field of the Invention
This invention relates to error checking and correction systems for memories for data processing systems. More particularly, it relates to an improvement in memory error checking systems in which errors which occur in the memory driving and reading logic, including the check bit generator, logic translators and the syndrome generator, might be separated from errors which occur in the memory.
2. Description of the Prior Art
Memory systems of various types have been developed through the years for use with data processing systems. Common to all memory systems utilized in binary data processing systems is the ability to record and read back some form or manifestation that can be distinguished between two possible states, one state indicating a binary zero and the other state indicating a binary one. These memory systems include memories that store data serially, such as on magnetic tapes, and memories that store data at addressable locations. The latter type of memories are often referred to as "random access" systems indicating that the data is capable of being specifically identified and retrieved through addressing. Addressable memories can include various types of structures that are well known. These include magnetic drums, magnetic disks, magnetic core memories, integrated circuit memories, as well as other more esoteric memory types.
More recently Dynamic Random Access Memory (DRAM) and Complementary-Metal-Oxide Semiconductor (CMOS) memories that require periodic refreshing of the memory contents have been employed for high speed memory access.
It has long been recognized that the integrity of the data bits that are stored and retrieved is critical to the accuracy of operations performed in the data processing system. The alteration of one bit in a data word can dramatically affect arithmetic calculations, or change the meaning of the recorded data. It was recognized that by associating an additional bit, called a "parity bit," with the binary bits comprising an addressable word, that erroneous data words could be detected.
Parity is, therefore, well known and simply involves summing, without the carry, the "1" bits in a data word and providing an additional parity bit that renders the total count across the data word, including the parity bit either odd or even. It is apparent that with a single parity bit in conjunction with a data word comprised of multiple number of bits, for example 36bits, multiple errors will defeat the parity system. As calculation rates increase, circuit sizes decrease and signal levels correspondingly are reduced. The likelihood of undetectable errors occurring is appreciably increased.
It has long been recognized in data transmission systems that by properly encoding data bits, multiple errors can be detected and corrected after transmission. The overhead for such additional accuracy, however, was the necessity of transmitting a larger number of bits since the error detection/correction bits had to be transmitted along with the data bits. Prior memory systems have been developed wherein the data word to be stored in an addressable memory location is encoded to provide Error Correction Code (ECC) signals. These signals are stored in the system's memory along with the bits of the data word.
Upon readout, the data bits read from an addressable memory location are again subjected to the generation of the same error correction code signal pattern, and the newly generated pattern is compared to the error correction code signals stored in the memory. If a difference is detected, it is determined that the data word is in error. Depending upon the encoding system utilized, it is possible to identify and correct one or more bit positions in the data word which were identified as being in error. The system overhead for the utilization of error correction code signals is the time necessary to generate them, the memory cells necessary to store them, and the time required to decode them at readout. These are the offsetting disadvantages to the advantages of recording and reading back data with a higher degree of accuracy and integrity than systems without such an error correction code system.
Even with the addition of the circuitry necessary to generate the error correction code signals and the additional memory cells necessary to store them, errors can occur in the generation of the error correction code signals through circuit faults, through the erroneous recording or read back of the error correction code signals, through memory cell failure, or through read/write circuit failure. Such failures can lead to the indication of erroneous data with the possibility of correct data bits being altered in the correction system, when, in fact, the error actually occurred in the error correction code signal handling. Systems have also been developed that utilize redundant circuits which perform various integrity checking functions at the expense of additional cost of hardware, together with an increased error-inducing probability due to circuit malfunction of the integrity checking circuit itself.
U.S. Pat. No. 4,531,213, "Memory Through Checking System with Comparison of Data Word Parity Before and After ECC Processing" issued Jul. 13, 1985 in the name of James H. Scheuneman, and is assigned to the assignee of the present invention. The invention of this patent is an improved memory system for use in a data processing system, wherein the memory is arranged for storing data words and error correction code signals associated therewith at addressable location. Through checking circuitry is employed for checking the operation of the error correction code circuitry. A parity generator is included in the system of the prior Scheuneman patent for generating the parity of a data word. The parity generator has circuitry for storing the parity bits in the memory that were generated with the associated data word along with the related error correction code signals.
When a data word is accessed, circuitry is provided for generating new error correction code signals and comparing the newly generated signals with the error correction code signals read from the memory device. The comparison circuitry of the prior Scheuneman patent includes error correction circuitry that functions to correct a predetermined number of detected errors within the data read from the memory device. Parity generating circuitry for generating a parity signal for the data word read out after correction, if correction is indicated, is provided.
This prior system has the capability of comparing the parity generated at readout with the parity stored along with the accessed data word for determining whether a data bit has been erroneously corrected due to a malfunction of the error correction code circuitry. The comparison circuitry provides an error indicating signal when the parity that is calculated at read out has a predetermined relationship to the parity signal stored with the accessed word.
A major problem in the use of Error Correcting Codes (ECC) is the testability of the ECC and supporting circuitry. The ECC may be effectively tested using special purpose test equipment, but this approach is usually too costly for other than the in-factory testing. A common method of field testing utilizes test software which reads and writes test patterns into the memory array and thereby inferentially tests the ECC. This technique is widely used despite the time consuming nature of the software testing. The greatest disadvantage of this technique is the necessary reliance upon assuming correct operation of the memory array. This assumption may be so unrealistic (i.e., probability of memory array failure may be so high) as to render the testing technique unacceptably unreliable.
The invention of U.S. Pat. No. 4,223,382, issued in the name of Lee T. Thorsrud and assigned to the assignee of the present invention, permits the cost advantages of software testing of ECC without reliance upon the use of the memory array in the testing process. The memory module of this patent has a semiconductor memory array and contains Error Correction Circuitry (ECC). The memory module also contains a status register which is used for control of various member functions and for indicating certain status information (e.g., error status, error logging, etc.). The status register may be accessed (i.e., written into and read from) as if it were an addressable location of the memory module whenever the memory module is placed into maintenance mode. A two position manual switch selects normal or maintenance mode. In maintenance mode one or more addresses are dedicated to accessing the status register. Therefore, the contents of the status register may be altered by placing the memory module into maintenance mode and writing via software into a dedicated address.